**Mandatory** for level I nodes with a decision matrix

Report the size for the decision matrix and the offset to its storage. The reported size is the number of decision matrix lines. The offset is the offset in the register address counter from 0x00 (See the register model in this document). If the size returned is zero the node does not have a decision matrix. A node without a decision matrix can also skip to implement this event but it's better if it returns a decision matrix size of zero. 

 | Data byte | Description | 
 | :---------: | ----------- | 
 | 0  | Matrix size (number of rows). Zero for a device with no decision matrix. | 
 | 1 | Offset in register space. | 
 | 2 | Optional page start MSB ( Interpret as zero if not sent ) | 
 | 3 | Optional page start LSB ( Interpret as zero if not sent ) | 
 | 4 | Optional page end MSB ( Interpret as zero if not sent ) Deprecated. Set to zero. | 
 | 5 | Optional page end LSB ( Interpret as zero if not sent ) Deprecated. Set to zero. | 
 | 6 | For a Level II node this is the size of a decision matrix row. **deprecated** See info below | 

The decision matrix can as noted be stored in paged registers and if so it must be accessed with the paged read/write. 

**Level II**: Level II nodes should respond with [CLASS2_PROTOCOL, TYPE=VSCP2_TYPE_PROTOCOL_GET_MATRIX_INFO_RESPONSE](./class2.protocol#type34)

